Configurable addressing for multiple chips in a package

ABSTRACT

A first semiconductor chip is provided. The first semiconductor chip is operable to be incorporated along with at least a second semiconductor chip of the same type into an integrated circuit device within in a single package. The integrated circuit device has a common address path for the first and second semiconductor chips. The first semiconductor chip includes a configurable addressing circuit operable to be configured so that the first semiconductor chip responds to a predetermined range of addresses in the common address path of the integrated circuit device, to decode an address conveyed in the common address path of the integrated circuit device, and to generate a selection signal if the address conveyed in the common address path falls within the predetermined range of addresses.

FIELD OF THE INVENTION

The present invention relates to integrated circuit (IC) devices, and inparticular, configurable addressing for multiple chips in a package.

BACKGROUND OF THE INVENTION

In the field of integrated circuit (IC) devices, several semiconductordie (commonly referred to as “chips”) can be combined into a singleprotective package. For some applications, a plurality of the chips putinto a single package can be the same type, such as, for example, memoryor logic. This allows for increased functional capacity using readilyavailable chips.

For integrated circuit devices having multiple chips of the same type inone package, it may be desirable during operation to access a specificone of such chips within the package for inputting or retrievingdata/information. With previously developed techniques, a specific chipis accessed using one or more chip select signals, which select thedesired chip. Such previously developed techniques, however, can beproblematic. A user of a multiple-chip integrated circuit device mustgenerate the chip select signal, either by programming or hardwiringelectronic components which interface with the integrated circuitdevice. Furthermore, provision must be made to keep track of whichinformation/data is or should be input or retrieved from which chip inthe device. Also, the functional elements (e.g., logic or memory) on theseparate chips cannot be viewed as a uniform group of elements, whichare accessible as a whole. Rather, the elements on a first chip must beconsidered and treated as a first group, the elements on a second chipmust be considered and treated as a second group, and so on. Thiscomplicates the use of and interaction with the multiple-chip integratedcircuit device.

SUMMARY OF THE INVENTION

The disadvantages and problems associated with previously developedschemes and techniques for accessing multiple chips of the same kind ina single package have been substantially reduced or eliminated using thepresent invention.

In accordance with an embodiment of the present invention, a firstsemiconductor chip is provided which is operable to be incorporatedalong with at least a second semiconductor chip of the same type into anintegrated circuit device within a single package. The integratedcircuit device has a common address path for the first and secondsemiconductor chips. The first semiconductor chip includes an optionlogic circuit operable to generate a configuration signal for causing anaddress decode circuit to respond to a predetermined range of addressesconveyed in the common address path of the integrated circuit device.The address decode circuit is in communication with the option logiccircuit. The address decode circuit is operable to decode an addressconveyed in the common address path of the integrated circuit deviceusing the configuration signal and to generate a selection signal forselecting the first semiconductor chip if the address falls within thepredetermined range of addresses.

In accordance with another embodiment of the present invention, a methodis provided for configurable addressing of a first semiconductor chipincorporated along with at least a second semiconductor chip of the sametype into an integrated circuit device within a single package. Theintegrated circuit device has a common address path for the first andsecond semiconductor chips. The method includes: generating aconfiguration signal for causing the first semiconductor chip to respondto a predetermined range of addresses conveyed in the common addresspath of the integrated circuit device; and generating a selection signalfor selecting the first semiconductor chip if an address conveyed in thecommon address path of the integrated circuit device falls within thepredetermined range of addresses.

In accordance with yet another embodiment of the present invention, anintegrated circuit device having a common address path is provided. Theintegrated circuit device includes a multi-chip module substrate. Aplurality of semiconductor chips of the same type are attached to themulti-chip module substrate. Each semiconductor chip comprises arespective configurable addressing circuit for causing the semiconductorchip to respond to a respective predetermined range of addresses,wherein each semiconductor chip is selected by an address conveyed inthe common address path of the integrated circuit device if the addressfalls within the respective predetermined range of addresses for thesemiconductor chip

In accordance with still another embodiment of the present invention, anintegrated circuit device includes a multi-chip module substrate. Aplurality of semiconductor chips of the same type are attached to themulti-chip module substrate. A common address path is provided for theplurality of semiconductor chips. Each semiconductor chip comprises arespective plurality of functional elements, each functional elementseparately addressable by a respective address. Each semiconductor chipalso includes a respective configurable addressing circuit for causingthe semiconductor chip to respond to any address within a respectivepredetermined range of addresses. This respective predetermined range ofmay comprise the respective addresses for each functional element of thesemiconductor chip, wherein said any address within the respectivepredetermined range of addresses is conveyed in the common address pathof the integrated circuit device.

In accordance with another embodiment of the present invention, anintegrated circuit device includes a multi-chip module substrate. Aplurality of semiconductor chips of the same type can be attached to themulti-chip module substrate. A common address path for the plurality ofsemiconductor chips is provided. Each semiconductor chip may comprise arespective plurality of functional elements and respective configurableaddressing circuit. Each functional element can be separatelyaddressable by a respective address. The respective configurableaddressing circuits cause the semiconductor chip to respond to anyaddress within a respective predetermined range of addresses. Therespective predetermined range of addresses comprises the respectiveaddress for each functional element of the semiconductor chip, whereinsaid any address within the respective predetermined range of addressesis conveyed in the common address path of the integrated circuit device.

In accordance with still yet another embodiment of the presentinvention, a decode circuit is provided for a first semiconductor chipwhich is operable to be incorporated along with at least a secondsemiconductor chip of the same type into an integrated circuit devicewithin a single package. The integrated circuit device has a commonaddress path for the first and second semiconductor chips. The decodecircuit is operable to generate a selection signal for selecting thefirst semiconductor chip if an address conveyed in the common addresspath falls within a predetermined range of addresses.

In accordance with yet another embodiment of the present invention, anoption logic circuit is provided for a first semiconductor chip operableto be incorporated along with at least a second semiconductor chip ofthe same type into an integrated circuit device within a single package.The integrated circuit device has a common address path for the firstand second semiconductor chips. The option logic circuit is operable tobe configured so that the first semiconductor chip responds to apredetermined range of addresses conveyed in the common address path ofthe integrated circuit device. The option logic circuit is operable togenerate a configuration signal for causing the first semiconductor chipto be selected if an address conveyed in the common address path fallswithin the predetermined range of addresses.

In accordance with yet another embodiment of the present invention, afirst semiconductor chip is provided. The first semiconductor chip isoperable to be incorporated along with at least a second semiconductorchip of the same type into an integrated circuit device within in asingle package. The integrated circuit device has a common address pathfor the first and second semiconductor chips. The first semiconductorchip includes a configurable addressing circuit operable to beconfigured so that the first semiconductor chip responds to apredetermined range of addresses in the common address path of theintegrated circuit device, to decode an address conveyed in the commonaddress path of the integrated circuit device, and to generate aselection signal if the address conveyed in the common address pathfalls within the predetermined range of addresses.

In accordance with another embodiment of the present invention, a methodis provided for configurable addressing of a first semiconductor chipincorporated along with at least a second semiconductor chip of the sametype into an integrated circuit device within a single package. Theintegrated circuit device has a common address path for the first andsecond semiconductor chips. The method comprises: configuring the firstsemiconductor chip to respond to a predetermined range of addresses inthe common address path of the integrated circuit device; decoding anaddress conveyed in the common address path of the integrated circuitdevice; and generating a selection signal if the address conveyed in thecommon address path falls within the predetermined range of addresses.

Important technical advantages of the present invention are readilyapparent to one skilled in the art from the following figures,descriptions, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For more complete understanding of the present invention and for furtherfeatures and advantages, reference is now made to the followingdescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 illustrates an integrated circuit device, according to anembodiment of the present invention.

FIG. 2 illustrates how multiple chips within a package can be viewed asa single chip with application of the present invention.

FIG. 3A is a schematic diagram in partial block form for animplementation of an option logic circuit, according to an embodiment ofthe present invention.

FIG. 3B is a schematic diagram for an alternate implementation of a bondoption circuit.

FIG. 4 is a schematic block diagram for an implementation of aconfiguration decode circuit, according to an embodiment of the presentinvention.

FIG. 5 is a schematic diagram for an implementation of a decode circuit,according to an embodiment of the present invention.

FIG. 6 is a schematic diagram for an implementation of a pass gate.

FIG. 7 is a schematic diagram for an implementation of delay hold timecircuit, according to an embodiment of the present invention.

FIG. 8 is a schematic diagram for an implementation of row address latchcircuit, according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention and their advantagesare best understood by referring to FIGS. 1 through 8 of the drawings.Like numerals are used for like and corresponding parts of the variousdrawings.

Multiple Chips in a Package

FIG. 1 illustrates an integrated circuit device 10, according to anembodiment of the present invention. Integrated circuit device 10 may becontained in a single protective package (e.g., plastic, ceramic,micro-ball grid array (MBGA), or chip scale package (CSP)) with suitableleads or other connecting points extending therefrom (not shown). Asdepicted, integrated circuit device 10 may comprise a multi-chip module(MCM) substrate 11 having multiple semiconductor dies or “chips” 12 ofthe same type attached thereto. It should be understood, however, thatthe present invention is not limited to this particular context, but mayhave broader applicability. MCM substrate 11 may have bonding pads (notexpressly shown) for conveying signals into and out of integratedcircuit device 10.

Semiconductor chips 12 are separately labeled 12 a, 12 b, 12 c, and 12d. Although four chips 12 are depicted for this embodiment, it should beunderstood that more or less chips 12 may be present in otherembodiments. Each semiconductor chip 12 can be implemented as a separatemonolithic, semiconductor die. In one embodiment, for example, eachsemiconductor chip 12 can be an integrated circuit memory chip includingdynamic random access memory (DRAM), static random access memory (SRAM),non-volatile random access memory (NVRAM), and read only memory (ROM),such as erasable programmable ROM (EPROM), electrically erasableprogrammable ROM (EEPROM), and flash memory. In another embodiment, eachsemiconductor chip 12 can be a logic chip or device such as, forexample, a field programmable gate array (FPGA), programmable logicdevice (PLD), complex programmable logic device (CPLD), or other logicdevice.

Each semiconductor chip 12 may include a plurality of functionalelements for performing memory functions, logic functions, or any othersuitable functions. In one embodiment, the functional elements on thevarious semiconductor chips 12 can be separately addressable. Functionalelements for memory chips can be individual memory cells, blocks ofmemory cells, or arrays of memory cells. Functional elements for a logicdevice can be addressable logic function blocks.

The semiconductor chips 12 are attached to MCM substrate 11, and may beelectrically connected to bonding pads on the MCM substrate 11.Semiconductor chips 12 may exchange data and information with otherelectronic components internal to integrated circuit device 10. Forexample, semiconductor chips 12 may communicate with an applicationspecific integrated circuit (ASIC) 15, which can also be attached to MCMsubstrate 11. Furthermore, semiconductor chips 12 may exchange data andinformation with electronic components connected and external tointegrated circuit device 10. Such an external component can be, forexample, a separately packaged microprocessor. In some situations, thedata/information exchanged with semiconductor chips 12 may be desirablydirected, transferred, or communicated to or obtained from a particularone of the semiconductor chips 12.

According to an embodiment of the present invention, a separateconfigurable addressing circuit 13 is provided on each semiconductorchip 12 so that the individual chips 12 can be accessed via addressingsignals, rather than with a chip select signal. In one embodiment,configurable addressing circuits 13 provide an option, which may or maynot be enabled, for accessing the respective chips 12. Configurableaddressing circuits 13 are separately labeled 13 a, 13 b, 13 c, and 13d, and may each be connected to one or more bonding pads on MCMsubstrate 11. With configurable addressing circuits 13, addressingsignals may be used to identify or specify a particular semiconductorchip 12 with which to communicate for the transfer or exchange of dataand information. That is, address signals in a normal address pathcommon to at least a portion, up to all, of semiconductor chips 12 areused to select individual chips 12. This is advantageous in that anelectronic component interacting with integrated circuit device 10 isnot required to know with which semiconductor chip 12 it needs tocommunicate for inputting or extracting data/information. Nor is such anexternal electronic component required to support one or more chipselect signals to specifically identify a particular semiconductor chip12 in integrated circuit device 10.

Furthermore, configurable addressing circuits 13 allow the functionalelements on all chips 12 to be presented as a uniform block of elements(e.g., logic or memory) which can be interfaced via a single set ofaddressing signals. This provides flexibility in implementation at thepackage level—i.e., more or less chips 12 can be used in integratedcircuit device 10 depending on the functional capability desired.Configurable addressing circuits 13 can thus be used to provide aperceived increase in functional capability (e.g., four times morememory capacity) using a multiple of chips 12, but without requiring auser of integrated circuit device 10 to provide or support a chip selectsignal.

Each configurable addressing circuit 13 can be configured so that therespective chip 12 on which the circuit 13 is contained responds to aparticular range of addresses which may appear on the common addresspath. This configuration can be accomplished via a bonding option, afuse option, an anti-fuse option, programming, or any other suitablemechanism for configuration. Actions for configuring configurableaddressing circuit 13 are represented symbolically by XO0, XO1, XO2, andXO3 in FIG. 1. Each configuration action XO0, XO1, XO2, and XO3comprises one or more actions for configuring a respective configurableaddressing circuit 13 to be accessed by a particular range of addresses.In one embodiment, each programming action XO0, XO1, XO2, or XO3includes a respective first and second selection actions XOPTS0, XOPTS1and a respective enabling action XOPTE. For a bonding option, aconfiguration action can be bonding a pad on a chip 12 to either ground(GND) or a voltage supply (VDD). For a fuse option, a configurationaction can be blowing a fuse. For an anti-fuse option, a configurationaction can be programming an anti-fuse. For a programming option, aconfiguration action can be providing a programming signal, for example,via ASIC 15.

Each configurable addressing circuit 13 may receive address signals XAj,XA(j+1). The address signals XAj, XA(j+1) can be a part of a group ofaddress signals XA0-XAn which are used for accessing elements (e.g.,logic or memory) contained in any of the semiconductor chips 12. Addresssignals XA0-XAn appear on a normal address path common to all chips 12.Address signals XAj, XA(j+1) may represent the most significant bits(MSB), the least significant bits (LSB), or any other bits of addresssignals XA0-XAn. A particular combination of values for address signalsXAj, XA(j+1) essentially function to address a particular chip 12 to theexclusion of addressing the other chips 12. Address signals XAj, XA(j+1)can be generated external to chips 12 and input to chips 12 via one ormore bonding pads. Each configurable addressing circuit 13 can beconfigured with respective selection actions XOPTS0, XOPTS1 so that therespective chip 12 is addressed by a particular combination of valuesfor address signals XAj, XA(j+1). Enable action XOPTE enables theconfigurable addressing circuit 13 on the respective semiconductor chip12. If configurable addressing circuit 13 is enabled, then therespective chip 12 “sees” the address bits provided by address signalsXAj, XA(j+1) and may generate a respective internal selection signal(Y0, Y1, Y2, or Y3) for the chip in response to an address which fallswithin the range for which that chip 12 is configured. If theconfigurable addressing circuit 13 is not enabled on a particular chip12, then the chip will ignore the address bits provided by addresssignals XAj, XA(j+1).

An embodiment of one scheme for the configuration actions and addressingsignals for chips 12 (in which configuration addressing circuits 13 areimplemented as bonding options) is provided in the following Table 1:

TABLE 1 Bonding Chip Value of Value for Bonding Bonding AddressedXA(j + 1) of XAj XOPTE for XOPTS1 for XOPTS0 Chip 0 0 0 GND NB NB Chip 10 1 GND NB GND Chip 2 1 0 GND GND NB Chip 3 1 1 GND GND GND

In Table 1, “GND” indicates bonding to ground, and “NB” indicates “notbonded.” Alternatively, instead of being “not bonded,” bonding could beto VDD. Each option logic circuit 14 may output one or moreconfiguration signals.

The addressing scheme provided in Table 1 can support an integratedcircuit device 10 having three or four chips 12. It should beunderstood, however, that in general the number of addressing signalsused for addressing the different chips 12 in integrated circuit device10 depends on the number of chips provided. For example, in otherembodiments, if integrated circuit device 10 contains only two chips 12,then a single addressing signal is sufficient; if integrated circuitdevice 10 contains from five to eight chips 12, then three addressingsignals are needed; if integrated circuit device contains from nine tosixteen chips, then four addressing signals are needed; and so on.

As depicted, for each semiconductor chip 12, configurable addressingcircuit 13 comprises an option logic circuit 14 (separately labeled 14a, 14 b, 14 c, and 14 d) and a configuration decode circuit 16(separately labeled 16 a, 16 b, 16 c, and 16 d).

Each option logic circuit 14 can be configured with one or morerespective configuration actions XOPST0, XOPTS1, so that the respectivesemiconductor chip 12 responds to a particular range of addresses. Theseaddresses may be provided to integrated circuit device 10 via addressingsignals, which may include address signals XAj and XA(j+1). Option logiccircuits 14 can be implemented as bonding options, fuse options,anti-fuse options, software programmed, or any other suitableimplementation. Each option logic circuit 14 may generate one or moreconfiguration signals.

Each configuration decode circuit 16 is coupled to or in communicationwith the option logic circuit 14 on the same semiconductor chip 12 andreceives the configuration signals therefrom. The configuration signalscause the configuration decode circuit 16 to be responsive to therespective range of addresses. Thus, if an address conveyed at least inpart by the address signals XAj, XA(j+1) falls within the particularrange of addresses for which the respective configurable addressingcircuit 13 has been configured, the configuration decode circuit 16generates a respective internal selection signal (Y0, Y1, Y2, or Y3) forthe semiconductor chip 12 on which it is incorporated.

In practice, the configurable addressing circuit 13 on eachsemiconductor chip 12 may be configured to respond to a respective rangeof addresses. This is accomplished by performing respectiveconfiguration actions XOPTS0, XOPTS1, XOPTE to the option logic circuit14 on each respective chip 12. Each option logic circuit 14 may thengenerate one or more configuration signals which are provided to therespective configuration decode circuit 16. After configuration,integrated circuit device 10 may be used in normal operating mode.During the normal operating mode, address signals XA0-XAn (includingXAj, XA(j+1)) are provided in a normal address path common to at least aportion of chips 12 to address various elements (e.g., logic or memory)in integrated circuit device 10. These elements may be part of one ormore of chips 12. The configuration decode circuits 16 on all chips 12in integrated circuit device 10 receive these address signals XA0-XAn.If the address signals are conveying an address which falls within therange for which a particular configurable addressing circuit 13 has beenconfigured, the respective configuration decode circuit 16 will output arespective internal selection signal Y0, Y1, Y2, or Y3 for theparticular chip 12. This causes the chip 12 to be accessible, and thusdata/information can be input into or retrieved from one or moreelements on the chip 12.

Addressing View

FIG. 2 illustrates how multiple chips within a package can be viewed asa single chip with application of the present invention. Withconfigurable addressing circuits 13, chips 12 in integrated circuitdevice can be treated as a uniform block of functional elements whichare accessed with a set of addressing signals XA0-XAn (of which XAj,XA(j+1) may be part) and without the need for external chip selectsignals. As depicted, if each chip 12 comprises 1K of memory which isaddressable by ten address bits A0-A9, then four chips 12 provide 4K ofmemory which can be addressed with twelve address bits A0-A11. In thisexample, addressing signals XAj, XA(j+1) may convey address bits A10,A11, respectively. Any electronic component interacting with the fourchips 12, each with 1K of memory capacity, should support addresssignals for a twelve-bit address, but does not need to support, provideor generate a separate chip select signal.

Option Logic Circuit

FIG. 3A illustrates a schematic diagram in partial block form for animplementation of an option logic circuit 14, according to an embodimentof the present invention. Option logic circuit 14 can be incorporated ona semiconductor chip 12 and may be coupled to or in communication with arespective configuration decode circuit 16 on the same chip. Asdepicted, option logic circuit 14 comprises a number of bond optioncircuits 18 (separately labeled 18 a, 18 b, and 18 c).

Each bond option circuit 18 generally functions to implement a bondingoption for the semiconductor chip 12 on which bond option circuit 18 isincorporated. A bond option circuit 18 may be bonded out via arespective configuration action XOPTx to produce a respective internalconfiguration action signal OPTx in response. As depicted, in oneembodiment, the configuration actions can include selection actionsXOPTS0, XOPTS1 and an enable action XOPTE. The selection actions XOPTS0,XOPTS1 configure the respective semiconductor chip 12 to respond to aparticular range of addresses. The enable action XOPTE enables the useof configurable addressing circuit 13 on the respective chip 12.

FIG. 3B provides a detailed exemplifying schematic implementation forbond option circuit 18 a, but it should be understood that the otherbond option circuits 18 b and 18 c can be implemented in substantiallythe same way. Referring to the detailed implementation for bond optioncircuit 18 a, in one embodiment, each bond option circuit 18 maycomprise transistors 20, 22, 24, and inverter gates 26, 28, 30, 32.Transistors 20 and 22 can be N-type transistors with drains coupled toan input terminal for bond option circuit 18. The input terminal isattached to a bonding pad (which can be bonded to ground, voltagesupply, or left unbonded, depending on the respective configurationaction XOPTS0, XOPTS1, or XOPTE). The source of each transistor 20 and22 is coupled to ground. The gate of transistor 20 receives power PWR,and the gate of transistor 22 is coupled to VDD.

Inverter gates 26, 28, 30, and 32 are coupled in series or cascadearrangement from the input terminal. Transistor 24 can be a P-typetransistor having a source coupled to VDD, a drain coupled to the outputterminal of inverter gate 26 (which is also the input terminal forinverter gate 28). The gate of transistor 24 is coupled to the outputterminal of inverter gate 28 (which is also the input terminal forinverter gate 30). The output of bond option circuit 18 (which may beconfiguration signal OPTS0, OPTS1, or OPTE) appears at the outputterminal.

It should be understood that the relationships between the configurationactions and the configuration signals described with reference to theembodiments depicted herein are arbitrary; in other embodiments, therelationships could be different. Furthermore, it should be understoodthat in other embodiments, rather than being implemented as a bondingoption, option logic circuit 14 can be implemented as a fuse option, ananti-fuse option, a programming option, or any other suitableimplementation. For a programming option, programming can beaccomplished via an ASIC, such as, for example, ASIC 14 shown in FIG. 1.

In operation, input terminal of bond option circuit 18 is bonded out toground or a supply voltage (or left unbonded). Power may be applied atthe gate terminal of transistor 20. If the input terminal of bond optioncircuit 18 is bonded to supply voltage, a high value appears at theinput terminal. This propagates through the inverter gates 26, 28, 30,and 32 so that the value of the signal output by inverter gate 32 is ahigh. The high value output by inverter gate 32 is output from bondoption circuit 18 as the value for the respective configuration signal.Alternatively, if the input terminal of bond option circuit 18 is bondedto ground, a low signal appears at the input terminal. This propagatesthrough bond option circuit 18 so that the value of the signal output byinverter gate 32 is low. This low value is output from bond optioncircuit 18 as the value for the respective configuration signal. Theconfiguration signal for bond option circuit 18 is provided to arespective configuration decode circuit 16 so that the circuit 16 mayrespond to a particular range of addresses.

FIG. 3B is a schematic diagram for an alternate implementation of a bondoption circuit 18. In this embodiment, as depicted, bond option circuit18 may comprise transistors 33, 34, and 35 and inverter gates 36, 37,and 38. Each of transistors 33 and 34 can be P-type transistors withsources coupled to VDD and drains coupled to an input terminal forcircuit 18. The gate of transistor 33 receives power PWR and the gate oftransistor 34 is connected to the output of inverter gate 36. Invertergates 36, 37, and 38 are connected in cascade arrangement. Transistor 35can be an N-type transistor. The drain of transistor 35 is coupled tothe output of inverter gate 36, and the source is connected to groundGND. The gate of transistor 35 is connected to the output of invertergate 37. The output of inverter gate 38 constitutes the output for bondoption circuit 18 in this embodiment.

Configuration Decode Circuit

FIG. 4 is a schematic block diagram for an implementation ofconfiguration decode circuit 16, according to an embodiment of thepresent invention. Configuration decode circuit 16 may be incorporatedon a semiconductor chip 12 and coupled to or in communication with arespective option logic circuit 14. When the configurable addressingcircuit 13 is enabled and bonded, configuration decode circuit 16responds to a particular range of addresses conveyed by one or moreexternal address signals XA0-XAn. As depicted, configuration decodecircuit 16 includes a decode circuit 40, a delay hold time circuit 42, aflip flop 43, and a row address latch circuit 44.

Decode circuit 40 receives configuration signals OPTS0, OPTS1, and OPTEwhich are generated by the respective option logic circuit 14. Decodecircuit 40 also receives the externally generated address signals XAj,XA(j+1). Decode circuit 40 generally functions to decode the variousconfiguration signals OPTS0, OPTS1, and OPTE and address signals XAj,XA(j+1) to determine whether the chip 12 on which configuration decodecircuit 16 is incorporated should be accessed in response. Decodecircuit 40 outputs an internal selection signal SELECT.

Delay hold time circuit 42 is coupled to or in communication with decodecircuit 40, and receives the address ADDR signal therefrom. Delay holdtime circuit 42 generally functions to delay the internal selectionsignal.

Flip flop 43 is coupled to or in communication with delay hold timecircuit 42. Flip flop 43 can be a D flip flop. Flip flop 43 receives thedelayed internal selection signal from delay hold time circuit 42. Flipflop 43 also receives a clock CLK signal. When the CLK signal goes high,flip flop 43 passes the delayed internal selection signal.

Row address latch circuit 44 is coupled to or in communication with flipflop 43, and receives the delayed selection signal. Row address latchcircuit 44 also receives a row address latch signal RAL. Row addresslatch circuit 44 generally functions to latch the internal selectionsignal so that it can be used for addressing elements within the chip12.

Decode Circuit

FIG. 5 is a schematic diagram for an implementation of decode circuit40, according to an embodiment of the present invention. In general,decode circuit 40 functions to generate an internal selection signalSELECT for selecting the chip 12 on which it is incorporated dependingon how configurable addressing circuit 13 has been configured to respondto externally generated address signals XAj, XA(j+1). Configuration isachieved with configuration signals OPTS0, OPTS1 generated by arespective option logic circuit 14. The values of configuration signalsOPTS0, OPTS1 depend on the configuration (e.g., bonding) options chosen.Decode circuit 40 will output a value for internal selection signalSELECT indicating that the semiconductor chip 12 has been addresseddepending on the particular combination of values for OPTS0, OPTS1,OPTE, XAj, and XA(j+1). It should be understood that the relationshipdescribed herein between the externally generated address signals andthe configuration signals is arbitrary, and in other embodiments, couldbe different. As shown, in one embodiment, decode circuit 40 comprisesinverter gates 42, 46, 48, 52, buffers 44, 50, pass gates 54,56, 58, 60,and an AND gate 62.

Inverter gate 42 receives configuration signal OPTS0 at its inputterminal. Pass gate 54 is enabled by the inverse of the configurationsignal OPTS0 and the output signal from inverter gate 42. Buffer 44 isenabled by the configuration signal OPTE and receives the externallygenerated address signal XAj at its input terminal. The output signalfrom buffer 44 is applied at the input terminal of pass gate 54 and theinput terminal of inverter gate 46. Pass gate 56 is enabled by theconfiguration signal OPTS0 and the inverse of the output signal frominverter gate 42. The output signal from inverter gate 46 is applied tothe input terminal of pass gate 56. Depending on the value ofconfiguration signal OPTS0, the value of external address signal XAj, orits inverse, will be passed by pass gate 54 or 56 to one input terminalof AND gate 62.

Inverter gates 48, 52, buffer 50, and pass gates 58, 60—which arecoupled in an arrangement similar to that for inverter gates 42, 46,buffer 44, and pass gates 54, 56—operate in substantially the samemanner so that the value of external address signal XA(j+1), or itsinverse, is input to the other input terminal of AND gate 62 dependingon the value of configuration signal OPTS1. AND gate 62 outputs theinternal selection signal SELECT. The internal selection signal SELECTmay cause the respective semiconductor chip 12 to be accessible.

Pass Gate

FIG. 6 illustrates an exemplary implementation for pass gate 64 whichcan be any of the pass gates described herein (e.g., pass gates 54, 56,58, and 60 shown in FIG. 4). As shown, pass gate 64 comprises a P-typetransistor 66 and an N-type transistor 68 with their sources and drainscoupled together. An enable signal C is applied to the gate oftransistor 66, and the inverse of the enable signal C is applied to thegate of transistor 68. An input terminal of pass gate 64 receives asignal A, and a signal B appears at an output terminal for pass gate 64.In operation, when the value of the enable C is low (and, consequently,the value of the inverse of the enable signal is high), the value of theinput signal A is passed through pass gate 64 as the value of signal B.

Delay Hold Time Circuit

FIG. 7 is a schematic diagram for an implementation of delay hold timecircuit 42, according to an embodiment of the present invention. Delayhold time circuit 42 generally functions to delay the internal selectionsignal SELECT for a predetermined amount of time. In one embodiment,this predetermined amount of time is programmable. As depicted, delayhold time circuit 42 includes inverter gates 70, 72, 74, 76, 78, 80, 82,84, 86, 88, and switches 98, 100, 102, 104, and 106.

The internal selection signal SELECT is applied at an input terminal ornode 108. Inverter gates 70, 72, 74, 76, 78, 80, 82, 84 are coupled inpairs. These pairs include inverter gates 70, 72, inverter gates 74, 76,inverter gates 78, 80, and inverter gates 82, 84. The pairs of invertergates may be programmably coupled in series, using respective switches98, 100, 102, 104, to provide an adjustable delay for the propagation ofthe internal selection signal SELECT from node 108 through delay holdtime circuit 42. In particular, each pair of inverter gates isassociated with a respective switch 98, 100, 102, or 104 which functionsto connect or add the pair of inverter gates to a delay chain, whichdelays the propagation of the internal selection signal SELECT. Switches98, 100, 102, and 104 couple the respective inverter gate pairs toeither node 108 or a preceding pair of inverter gates, therebyincreasing or decreasing the length of the delay chain. That is, theinverter gate pairs are added to or taken out of the delay chain byrespective switches 98, 100, 102, and 104. The inclusion of moreinverter gate pairs into the delay chain will increase the amount oftime by which internal selection signal SELECT is delayed whenpropagating through circuit 42. If more inverter gates are added to thedelay chain, there will be a longer delay for the propagation of theinternal selection signal SELECT. If less inverter gates are added tothe delay chain, there will be a shorter delay for the propagation ofthe internal selection signal SELECT. As depicted, only two invertergate pairs (which include inverter gates 78, 80, 82, and 84) are part ofthe delay chain.

As an alternative, if it is desired to minimize the delay for theinternal selection signal SELECT, then input terminal 108 may be coupledby switch 106 to the next portion of delay hold time circuit 42, therebyeffectively not using any of the delay chain which can be formed frominverter gates 70, 72, 74, 76, 78, 80, 82, 84.

This next portion of circuit 42 comprises inverter gates 86 and 88,which are connected in series. The output of the inverter gate 88comprises the output for delay hold time circuit 42, which is a delayedselection signal SELECT(D).

Row Address Latch Circuit

FIG. 8 is a schematic diagram of an implementation for row address latchcircuit 44, according to an embodiment of the present invention. Rowaddress latch circuit 44 may be incorporated on a semiconductor chip 12as part of configuration decode circuit 16. Row address latch circuit 44can be coupled to or in communication with a respective flip flop 43,which may also be part of the same configuration decode circuit 16. Ingeneral, row address latch circuit 44 functions to latch the delayedselection signal SELECT(D) so that it can be used for accessing elementsin the respective chip 12. As depicted, row address latch circuit 44comprises NAND gates 110, 112, 114 116, and inverter gates 118, 120.

Inverter gate 118 receives the row address latch signal RAL at its inputterminal. The output signal from inverter gate 118 is provided to oneinput terminal for each of NAND gates 110 and 114. Another inputterminal of NAND gate 110 receives the delayed selection signalSELECT(D) from the respective delay hold time circuit 42. Another inputterminal of NAND gate 114 receives the output signal from NAND gate 110.One input terminal of NAND gate 112 receives the output signal from NANDgate 110. Another input terminal of NAND gate 112 receives the outputsignal from NAND gate 116. One input terminal of NAND gate 116 receivesthe output signal from NAND gate 114, and the other input terminal ofNAND gate 116 receives the output from NAND gate 112. With thisarrangement, NAND gates 110, 112, 114, and 116 operate as a latchcircuit. When the row address latch signal RAL has a high value, thevalue of the internal selection signal SELECT from the respective flipflop 43 is latched.

Inverter gate 120 receives the output from NAND gate 116 at its inputterminal. Inverter gate 120 outputs the internal selection signalSELECT. This signal is then placed into the common address path for usein accessing a particular element (e.g., logic or memory) in thesemiconductor chip 12 on which the row address latch circuit 44 isincorporated. For example, in one embodiment, the internal selectionsignal SELECT may be generated as part of the logic for generating a rowaddress enable signal, which is applied to the pre-decoders.

With embodiments of the present invention, a user of an integratedcircuit device having multiple chips of the same type contained within asingle package is not required to specifically select from one of thechips during normal operation. Rather, similar elements (e.g., logic ormemory) contained in the various chips appear to the user as a uniformblock of elements which can be accessed with addressing signals providedin a normal address path common to all chips. The user is not requiredto provide and support chip select signals, nor to keep track of whatinformation/data should be stored or retrieved from each chip. Thisfacilitates operation and coding on the part of a user. Furthermore, anelectronic component interacting with the integrated circuit device isnot required to know with which semiconductor chip it needs tocommunicate for inputting or extracting data/information. Nor is such anexternal electronic component required to generate or support one ormore chip select signals to specifically identify a particularsemiconductor chip in the integrated circuit device.

The above-described embodiments of the present invention are merelymeant to be illustrative and not limiting. It will thus be obvious tothose skilled in the art that various changes and modifications may bemade without departing from this invention in its broader aspects.Therefore, the appended claims encompass all such changes andmodifications as fall within the true spirit and scope of thisinvention.

What is claimed is:
 1. A first semiconductor chip operable to beincorporated along with at least a second semiconductor chip of the sametype into an integrated circuit device within a single package, theintegrated circuit device having a common address path for the first andsecond semiconductor chips, the first semiconductor chip comprising: anoption logic circuit operable to generate a configuration signal forcausing an address decode circuit to respond to a predetermined range ofaddresses conveyed in the common address path of the integrated circuitdevice; and the address decode circuit in communication with the optionlogic circuit, the address decode circuit operable to decode an addressconveyed in the common address path of the integrated circuit deviceusing the configuration signal and to generate a selection signal forselecting the first semiconductor chip if the address falls within thepredetermined range of addresses, thereby enabling the firstsemiconductor chip to be selected in the integrated circuit devicewithin the single package.
 2. The first semiconductor chip of claim 1,wherein the option logic circuit is implemented as at least one of abond option, a fuse option, an anti-fuse option, or a programmingoption.
 3. The first semiconductor chip of claim 1, wherein the addressdecode circuit is operable to latch the selection signal.
 4. The firstsemiconductor chip of claim 3, wherein latching is in response to a rowaddress latch signal.
 5. The first semiconductor chip of claim 1,wherein the first and the second semiconductor chips each comprise amemory chip.
 6. The first semiconductor chip of claim 1, wherein thefirst and the second semiconductor chips each comprise a logic chip. 7.A method for configurable addressing of a first semiconductor chipincorporated along with at least a second semiconductor chip of the sametype into an integrated circuit device within a single package, theintegrated circuit device having a common address path for the first andsecond semiconductor chips, the method comprising: generating aconfiguration signal for causing the first semiconductor chip to respondto a predetermined range of addresses conveyed in the common addresspath of the integrated circuit device; and generating a selection signalfor selecting the first semiconductor chip if an address conveyed in thecommon address path of the integrated circuit device falls within thepredetermined range of addresses, thereby enabling the firstsemiconductor chip to be selected in the integrated circuit devicewithin the single package.
 8. The method of claim 7, wherein generatinga configuration signal comprises bonding an option logic circuit on thefirst semiconductor chip.
 9. The method of claim 7, wherein generating aconfiguration signal comprises blowing a fuse of an option logic circuiton the first semiconductor chip.
 10. The method of claim 7, whereingenerating a configuration signal comprises programming an antifuse ofan option logic circuit on the first semiconductor chip.
 11. The methodof claim 7, wherein generating a configuration signal comprisesprogramming an option logic circuit on the first semiconductor chip. 12.The method of claim 7, wherein generating a configuration signalcomprises enabling an option logic circuit on the first semiconductorchip.
 13. The method of claim 7, further comprising latching theselection signal.
 14. The method of claim 7, wherein generating aselection signal comprises decoding the address using the configurationsignal.
 15. An integrated circuit device within a single package havinga common address path, the integrated circuit device comprising: amulti-chip module substrate; and a plurality of semiconductor chips ofthe same type attached to the multi-chip module substrate, wherein eachsemiconductor chip comprises a respective configurable addressingcircuit for causing the semiconductor chip to respond to a respectivepredetermined range of addresses, wherein each semiconductor chip isselected by an address conveyed in the common address path of theintegrated circuit device if the address falls within the respectivepredetermined range of addresses for that semiconductor chip, therebyallowing any of the semiconductor chips to be selected in the integratedcircuit device within the single package.
 16. The integrated circuitdevice of claim 15, wherein each configurable addressing circuit isimplemented as at least one of a bond option, a fuse option, ananti-fuse option, or a programming option.
 17. The integrated circuitdevice of claim 15, wherein each semiconductor chip comprises a memorychip.
 18. The integrated circuit device of claim 15, wherein eachsemiconductor chip comprises a logic chip.
 19. The integrated circuitdevice of claim 15, wherein each configurable addressing circuitcomprises a respective option logic circuit operable to be configuredfor causing the respective semiconductor chip to respond to therespective predetermined range of addresses.
 20. The integrated circuitdevice of claim 15, wherein each configurable addressing circuitcomprises a respective address decode circuit operable to select therespective semiconductor chip if an address conveyed in the commonaddress path of the integrated circuit device falls within therespective predetermined range of addresses.
 21. An integrated circuitdevice within a single package comprising: a multi-chip modulesubstrate; a plurality of semiconductor chips of the same type attachedto the multi-chip module substrate; and a common address path for theplurality of semiconductor chips; wherein each semiconductor chipcomprises: a respective plurality of functional elements, eachfunctional element separately addressable by a respective address, and arespective configurable addressing circuit for causing the semiconductorchip to respond to any address within a respective predetermined rangeof addresses and without an external chip select signal, the respectivepredetermined range of addresses comprising the respective addresses foreach functional element of the semiconductor chip, wherein said anyaddress within the respective predetermined range of addresses isconveyed in the common address path of the integrated circuit device.22. The integrated circuit device of claim 21, wherein eachsemiconductor chip comprises a memory chip.
 23. The integrated circuitdevice of claim 21, wherein each semiconductor chip comprises a logicchip.
 24. The integrated circuit device of claim 21, wherein eachconfigurable addressing circuit is implemented as at least one of a bondoption, a fuse option, an anti-fuse option, or a programming option. 25.An option logic circuit for a first semiconductor chip operable to beincorporated along with at least a second semiconductor chip of the sametype into an integrated circuit device within a single package, theintegrated circuit device having a common address path for the first andsecond semiconductor chips, the option logic circuit operable to beconfigured so that the first semiconductor chip responds to apredetermined range of addresses conveyed in the common address path ofthe integrated circuit device, the option logic circuit operable togenerate a configuration signal for causing the first semiconductor chipto be selected in the integrated circuit device within the singlepackage if an address conveyed in the common address path falls withinthe predetermined range of addresses.
 26. The option logic circuit ofclaim 25, wherein the option logic circuit is implemented as a bondoption.
 27. The option logic circuit of claim 25, wherein the optionlogic circuit is implemented as a fuse option.
 28. The option logiccircuit of claim 25, wherein the option logic circuit is implemented asa an anti-fuse option.
 29. The option logic circuit of claim 25, whereinthe option logic circuit is implemented as a programming option.
 30. Afirst semiconductor chip operable to be incorporated along with at leasta second semiconductor chip of the same type into an integrated circuitdevice within a single package, the integrated circuit device having acommon address path for the first and second semiconductor chips, thefirst semiconductor chip comprising: an option logic circuit operable tobe configured for generating a configuration signal so that the firstsemiconductor chip responds to a predetermined range of addressesconveyed in the common address path of the integrated circuit device;and an address decode circuit in communication with the option logiccircuit, the address decode circuit operable to decode an addressconveyed in the common address path of the integrated circuit deviceusing the configuration signal and to generate a selection signal forselecting the first semiconductor chip in the integrated circuit devicewithin the single package if the address conveyed in the common addresspath falls within the predetermined range of addresses.
 31. The firstsemiconductor chip of claim 30, wherein the option logic circuit isimplemented as at least one of a bond option, a fuse option, ananti-fuse option, or a programming option.
 32. A method for configurableaddressing of a first semiconductor chip incorporated along with atleast a second semiconductor chip of the same type into an integratedcircuit device within a single package, the integrated circuit devicehaving a common address path for the first and second semiconductorchips, the method comprising: configuring the first semiconductor chipto respond to a predetermined range of addresses in the common addresspath of the integrated circuit device and without an external chipselect signal; decoding an address conveyed in the common address pathof the integrated circuit device; and generating a selection signal ifthe address conveyed in the common address path falls within thepredetermined range of addresses, thereby enabling the firstsemiconductor chip to be selected in the integrated circuit devicewithin the single package.